1. Technical Field
The invention disclosed and claimed herein generally relates to a method and apparatus for using a specified computer language to model a super scalar central processing unit (CPU). More particularly, the invention pertains to a method of the above type wherein operation of the CPU is characterized by a concurrently dispatched instruction stream, and the specified language is a sequential language such as C or C++. Even more particularly, the invention pertains to a method of the above type, wherein multiple concurrently operating functional units contained in the CPU are respectively synchronized to a virtual model master or base clock.
2. Description of Related Art
As is known by those of skill in the art, a Reduced Instruction Set Computer (RISC) is a microprocessor that is designed to perform a reduced number of types of computer instructions. This enables the microprocessor to operate at a higher speed. In the current super scalar RISC CPU design environment, a major problem is the verification of multiple dispatched Signal Instruction Multiple Data (SIMD) instruction streams. More particularly, a typical super scalar RISC CPU comprises a complicated concurrent operational machine, wherein every block unit functions simultaneously. Moreover, the internal timing of a RISC CPU is typically in accordance with a multiple stage pipelined operation.
It would be very desirable to use sequential language, such as C or C++, to model the multiple dispatched instruction stream of a RISC CPU. This could provide a useful tool for the verification of multiple dispatched SIMD instructions streams. However, the sequential nature of these types of compiled languages makes it rather difficult to use them to model the concurrent events that take place within a super scalar CPU. The concurrency problem is complicated by the addition of floating point instruction streams, since the floating point unit (FPU) in the CPU has separated instruction queues and execution engines. In addition, since the internal timing of the RISC CPU operates in the mode of a multiple stage pipelined operation, as noted above, the sequential execution nature of a compiled model language such as C or C++ cannot correctly model the CPU operation, with acceptable precision or accuracy to the clock standard.